Timing Analyzer reports the detailed information about the performance of your design compared with constraints in the Compilation Report panel.Save the constraints you specify in the GUI in an industry-standard Synopsys Design Constraints File ( parameter editor.
When you add a logic design file to the project, the Compiler automatically compiles that file as part of the project.
The Compiler synthesizes your logic design files to generate programming files for your target device. Specify constraints for clock characteristics, timing exceptions, and external signal setup and hold times before running analysis.
Except for the top-level of the design where permitted, ensure that your RTL does not depend on this type of parameter passing. Ensure that your RTL code does not use unsized constants for WYSIWYG instantiation.
For example, specify a sized literal, such as 2'b11, rather than '1.
Each revision captures a unique set of project settings and constraints, but does not capture any logic design file changes.
Use revisions to experiment with different settings while preserving the original.
config mid_config; design good_lib.mid; instance mid.sub_inst use good_lib.sub; endconfig module test (input a1, output b); mid_config mid_inst ( .a1(a1), .b(b)); // in other Quartus products preceding line would have been: //mid mid_inst ( .a1(a1), .b(b)); endmodule module mid (input a1, output b); sub sub_inst (.a1(a1), .b(b)); endmodule The stricter library binding requirement complies with VHDL language specifications and results in deterministic behavior.
This benefits team-based projects by avoiding unintentional name collisions. Synthesis in other Quartus software products supports passing parameters with this method.
Global definitions and directives are visible in all files.